The present application relates to semiconductor device fabrication. More particularly, the present application relates to semiconductor fin formation by using two sets of spacers having different etching characteristics in a sidewall image transfer (SIT) process.
As integrated circuits continue to scale downward in size, fin field effect transistors (FinFETs) are becoming increasingly attractive to be used in smaller nodes, e.g., the 22 nm node and beyond. FinFETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to meet the density targets of advanced nodes, semiconductor fins are typically formed utilizing a sidewall image transfer (SIT) process since the same provides sub-lithographic line widths (i.e., less than 40 nm). In a typical SIT process, spacers are formed on each sidewall of a mandrel structure that is formed on a topmost semiconductor material of a substrate. The mandrel structure is removed and the remaining spacers are used as an etch mask to etch the topmost semiconductor material of the substrate. The spacers are then removed after each semiconductor fin has been formed.
One problem that is associated with forming semiconductor fins at tight pitch is that the process window for cutting of unwanted semiconductor fins is quite narrow. More specifically, the space available between fins at a tight pitch decreases the process window for placement of a fin cut mask edge in between fins. As the pitch of the semiconductor fins decreases, it becomes difficult to remove unwanted semiconductor fins without adversely affecting adjacent device fins due to the process variation and small process margin of lithographic processes. As such, a method is needed that is capable of forming semiconductor fins in which the process window for cutting unwanted semiconductor fins is improved.